View AR0141CS2M00SUEA0-DPBR_8578210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ar0141cs: 1/4-inch digital image sensor features ? ar0141cs/d rev. 6, 4/16 en 1 ?semiconductor components industries, llc 2016, 1/4-inch digital image sensor ar0141cs datasheet, rev. 6 for the latest datasheet, please visit: www.onsemi.com features ? superior low-light performance ? latest 3.0 ? m pixel with on semiconductor dr-pix technology ? linear range capture ? 1.0 mp and 720p (16:9) images ? support for external mechanical shutter ? support for external led or xenon flash ? on-chip phase-locked loop (pll) oscillator ? integrated position-based color and lens shading correction ? slave mode for precise frame-rate control ? stereo/3d camera support ? statistics engine ? data interfaces: four-lane serial high-speed pixel interface (hispi) differential signaling (slvs and hivcm), or parallel ? auto black level calibration ? high-speed context switching ? temperature sensor applications ? video surveillance ? scanning ?industrial ?stereo vision ? 720p60 video applications general description the on semiconductor ar0141cs is a 1/4-inch cmos digital image sensor with an active-pixel array of 1280hx800v. it captures imag es in linear mode, with a rolling-shutter readout. it includes sophisticated cam- era functions such as in-pixel binning, windowing and both video and single frame modes. it is designed for low light scene performance. it is programmable through a simple two-wire serial interface. the ar0141cs produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and hd video. table 1: key parameters parameter typical value optical format 1/4-inch active pixels 1280(h) x 800(v) (entire array) pixel size 3.0 ? m x 3.0 ? m color filter array rgb bayer, monochrome, rgb-ir shutter type electronic rolling shutter and grr input clock range 6 C 50 mhz output clock maximum 148.5 mp/s (4-lane hispi) 74.25 mp/s (parallel) output serial hispi, 12-bit parallel 10-, 12-bit frame rate 720p 60 fps responsivity 4.0 v/lux-sec snr max 41 db max dynamic range up to 79 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.3 v - 0.6 v, 1.7 v - 1.9 v power consumption (typical) 326 mw (linear mode 1280x720 60 fps) operating temperature (ambient) -t a C30c to + 70 c package options 9x9mm 63-ball ibga
ar0141cs/d rev. 6, 4/16 en 2 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. fo r reference documenta- tion, including information on evaluation kits, please visi t our web site at www.onsemi.com. table 2: available part numbers part number product description orderable product attribute description ar0141cs2c00suea0-dp color ibga dry pack with protective film ar0141cs2c00suea0-dr color ibga dry pack without protective film ar0141cs2c00suead3-gevk color ibga demo3 kit ar0141cs2c00sueah-gevb color ibga headboard ar0141cs2m00suea0 - tpbr mono ibga tape and reel with protective film ar0141cs2m00suea0 - dpbr mono ibga dry pack with protective film ar0141cs2m00suead3-gevk mono ibga demo3 kit ar0141cs2m00sueah-gevb mono ibga headboard ar0141irsh00suea0-dr rgb-ir, ibga, product ion dry pack without protective film ar0141irsh00suea0d3-gevk rgb-ir, demo3 kit ar0141irsh00suea0h3-gevb rgb-ir, head board ar0141cssm21suea0-tpbr mono, ibga , 21 deg shift engineering sample
ar0141cs/d rev. 6, 4/16 en 3 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 .functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 differentiation from ar0141cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 pixel output interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 pixel sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 gain stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 data pedestals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 sensor pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 sensor readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 sensor frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 frame readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 changing sensor modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
ar0141cs/d rev. 6, 4/16 en 4 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor general description general description the on semiconductor ar0141cs can be operated in its default mode or programmed for frame size, exposure, gain , and other parameters. the default mode output is a 720p- resolution image at 60 frames per second (f ps). in linear mode, it outputs 12-bit raw data, using either the parallel or serial (hispi) output ports. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are ou tput on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0141cs includes additional features to allow application-specific tuning: windowing and offset, auto black level corr ection, and on-board temperature sensor. optional register information and histogra m statistic information can be embedded in the first and last 2 lines of the image frame. .functional overview the ar0141cs is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 mhz. the maximum output pixel rate is 148.5 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor. figure 1: block diagram user interaction with the sensor is throug h the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.1 mp active- pi xel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate digital gain and pedestal 12 12 bits parallel hispi 12 or 10 bits row noise correction black level correction pixel defect correction test pattern generator 12 adc data adaptive cd filter
ar0141cs/d rev. 6, 4/16 en 5 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor .functional overview incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correct ion and gain), and then through an analog- to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path correc tions and applies digital gain). figure 2: typical configuration: serial four-lane hispi interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. the parallel interface output pads can be left unco nnected if the serial output interface is used. 4. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay- out and design considerations. check the ar0141c s demo headboard schematics for circuit recom- mendations. 5. on semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. v dd _io v dd _slvs v dd _pll v dd v aa v dd v aa v aa _pix master clock (6C50 mhz) s data s clk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi power 1 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2 analog power 1 v aa _pix slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n v dd _slvs trigger oe_bar s addr shutter flash
ar0141cs/d rev. 6, 4/16 en 6 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor .functional overview figure 3: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. the serial interface output pads and v dd slvs can be left unconnected if the parallel output inter- face is used. 4. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay- out and design considerations. check the ar0141c s demo headboard schematics for circuit recom- mendations. 5. on semiconductor recommends that analog powe r planes are placed in a manner such that cou- pling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 7. the extclk input is limited to 6-50 mhz. v dd master clock (6-50 mhz) s data s clk test frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, v aa v aa _pix analog power 1 vdd_pll pll power 1 analog power 1 v aa _pix v dd _io v dd _pll v dd v aa trigger oe_bar a gnd s addr shutter flash
ar0141cs/d rev. 6, 4/16 en 7 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor .functional overview figure 4: 9 x 9 mm 63-ball ibga package table 3: ball descriptions, 9 x 9 mm, 63-ball ibga name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n. slvs0_p a3 output hispi serial da ta, lane 0, differential p. slvs1_n a4 output hispi serial data, lane 1, differential n. slvs1_p a5 output hispi serial da ta, lane 1, differential p. standby a8 input standby (active high) v dd _pll b1 power pll power. slvsc_n b2 output hispi serial ddr clock differential n. slvsc_p b3 output hispi serial ddr clock differential p. slvs2_n b4 output hispi serial data, lane 2, differential n. slvs2_p b5 output hispi serial data, lane 2, differential p. v aa b7, b8 power analog power. extclk c1 input external input clock. v dd _slvs c2 power 0.3v-0.6v or 1.7v - 1.9v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring v dd _slvs to 1.7 C 1.9v. slvs3_n c3 output hispi serial data, lane 3, differential n. slvs3_p c4 output hispi serial data, lane 3, differential p. a b c d e f g h top view (ball down) slvs0_n slvs0_p slvs1_n slvs1_p v dd standby v dd _pll slvs_cn slvsc_p slvs2_n slvs2_p v dd v aa v aa extclk v dd _ slvs slvs3_n slvs3_p d gnd v dd a gnd s addr s clk s data d gnd d gnd v dd v aa _pix v aa _pix line_ valid frame_ valid pixclk flash d gnd v dd _io nc d out 8 d out 9d out 10 d out 11 d gnd v dd _io test d out 4d out 5d out 6d out 7d gnd v dd _io trigger oe_bar d out 0d out 1d out 2d out 3d gnd v dd _io v dd _io reset_ bar 12 3 567 8 4 v dd a gnd nc reserved
ar0141cs/d rev. 6, 4/16 en 8 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor .functional overview d gnd c5, d4, d5, e5, f5, g5, h5 power digital ground. v dd a6, a7, b6, c6, d6 power digital power. a gnd c7, c8 power analog ground. s addr d1 input two-wire serial addres s select. 0: 0x20. 1: 0x30 s clk d2 input two-wire serial clock input. s data d3 i/o two-wire serial data i/o. v aa _pix d7, d8 power pixel power. line_valid e1 output asserted when d out line data is valid. frame_valid e2 output asserted when d out frame data is valid. pixclk e3 output pixel clock out. d out is valid on rising edge of this clock. v dd _io e6, f6, g6, h6, h7 power i/o supply power. d out 8 f1 output parallel pixel data output. d out 9 f2 output parallel pixel data output. d out 10 f3 output parallel pixel data output. d out 11 f4 output parallel pixel data output (msb) test f7 input. manufacturing test enable pin (connect to d gnd ). d out 4 g1 output parallel pixel data output. d out 5 g2 output parallel pixel data output. d out 6 g3 output parallel pixel data output. d out 7 g4 output parallel pixel data output. trigger g7 input exposure synchronization input. oe_bar g8 input output enable (active low). d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output. d out 2 h3 output parallel pixel data output. d out 3 h4 output parallel pixel data output. reset_bar h8 input asynchronous reset (active lo w). all settings are restored to factory default. nc e8 flash e4 output flash control output. nc e7 reserved f8 table 3: ball descriptions, 9 x 9 mm, 63-ball ibga (continued) name ibga pin type description
ar0141cs/d rev. 6, 4/16 en 9 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel data format pixel data format pixel array structure the ar0141cs pixel array consists of 1280 co lumns by 800 rows of optically active pixels.while the sensor's format is 1344 x 848 , additional active co lumns and active rows are included for use when horizontal or vert ical mirrored readout is enabled, to allow readout to start on the same pixel. the pixe l adjustment is always performed for mono- chrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity wi thin the active area. not all dummy pixels or barrier pixels can be read out. figure 5: pixel array description not to scale all dimensions in pixels unless otherwise stated 1348 ( 2+ 1344 + 2) active pixels total = 1348 total = 86 8 86 8 ( 8+ 2+ 4+ 848 +6 ) transport pixels 8
ar0141cs/d rev. 6, 4/16 en 10 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor differentiation from ar0141cs figure 6: rgb pixel color pattern detail (top right corner) - ar0141cs figure 7: rgb-ir pixel color patter n detail (top right corner) - aro141ir differentiation from ar0141cs the ar0141ir can be electrically differentiate d from the ar0141cs by reading bits 11:9 in r0x31fa. the ar0141ir contains a unique valu e of 4 in these bits. it is necessary to set r0x301a[5]=1 prior to reading r0x31fa[11:9]. active pixel (0,0) array pixel (0, 0) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction active pixel (0,0) array pixel (0, 0) row reado ut direction ir b ir b ir b r g r g r g r g r g r g r g r g r g r g r g r g ir b ir b ir b ir b ir b ir b ir b ir b ir b column readout direction
ar0141cs/d rev. 6, 4/16 en 11 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor differentiation from ar0141cs default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 6). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in de fault condition is that of pixel (0, 0). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 8. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced as shown in figure 8. figure 8: imaging a scene lens pixel (0,0) row readout order column readout order scene sensor (rear view)
ar0141cs/d rev. 6, 4/16 en 12 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel output interfaces pixel output interfaces parallel interface the parallel pixel data interface uses these output-only signals: ?frame_valid ?line_valid ?pixclk ?d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. ta ble 5 shows the recommended settings. when the parallel pixel data interface is in us e, the serial data output signals can be left unconnected. set reset_register [bit 12 (r0x301a[12] = 1)] to disable the serializer while in parallel output mode. output enable control when the parallel pixel data interface is enabled, its signals can be switched asynchro- nously between the driven and high-z under pi n or register control, as shown in table 4. configuration of the pixel data interface fields in r0x301a are used to configure the operation of the pixel data interface. the supported combinations are shown in table 5. table 4: output enable control oe_bar pin drive pins r0x301a[6] description disabled 0 interface high-z disabled 1 interface driven 1 0 interface high-z x 1 interface driven 0 x interface driven table 5: configuration of the pixel data interface serializer disable r0x301 a[12] parallel enable r0x301 a[7] description 0 0 power up default. serial pixel data interface and its clocks ar e enabled. transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface.
ar0141cs/d rev. 6, 4/16 en 13 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel output interfaces high speed serial pixel data interface the high speed serial pixel (hispi) interface uses four data lanes and one clock as output. ?slvsc_p ?slvsc_n ?slvs0_p ?slvs0_n ?slvs1_p ?slvs1_n ?slvs2_p ?slvs2_n ?slvs3_p ?slvs3_n the hispi interface supports three protocols, streaming-s, streamin g-sp, and packetized sp. the streaming protocols conform to a stan dard video application where each line of active or intra-frame blanking provided by th e sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. these protocols are further de scribed in the high-speed se rial pixel (hispi) interface protocol specification v1.50.00. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) cl ock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 9 shows the configuration between the hispi transmitter and the receiver. figure 9: hispi transmitter and receiver interface block diagram a camera containing the hispi transmitter a host (dsp) containing the hispi receiver dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 tx phy0 rx phy0 dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0
ar0141cs/d rev. 6, 4/16 en 14 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel output interfaces hispi physical layer the hispi physical layer is partitioned into bl ocks of four data lanes and an associated clock lane. any reference to the phy in the re mainder of this document is referring to this minimum building block. the phy will serialize 12-bit data words and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of the clock. figure 10 shows bit transmission. in this example, the word is transmitted in order of msb to lsb. the receiver latches data at the rising and falling edge of the clock. figure 10: timing diagram dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the rece iver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa- tion. figure 11: block diagram of dll timing adjustment c p dn . . msb lsb txpost dp cn 1 ui txpre delay delay delay delay delay data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3 clock_del[2:0] data0_del[2:0] data1_del[2:0] data2_del[2:0] data3_del[2:0]
ar0141cs/d rev. 6, 4/16 en 15 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel output interfaces figure 12: delaying the cl ock with respect to data figure 13: delaying data with respect to the clock hispi protocol layer the hispi protocol is described in the hispi protocol specification document. datan (datan_del = 000) cp (clock_del = 000) cp (clock_del = 001) cp (clock_del = 010) cp (clock_del = 011) cp (clock_del = 100) cp (clock_del = 101) c p (clock_del = 110) cp (clock_del =111) increasing clock_del [2:0] increases clock delay 1 ui 1 ui t dllstep cp ( clock_del = 000) datan (datan_del = 000) datan(datan_del = 001) datan(datan_del = 010) datan(datan_del = 011) datan(datan_del = 100) datan(datan_del = 101) datan(datan_del = 110) datan(datan_del = 111) increasing datan_del [2:0] increases data delay
ar0141cs/d rev. 6, 4/16 en 16 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel sensitivity serial configuration the serial format should be configured using r0x31ac. re fer to the ar0141cs register reference document for more de tail regarding this register. the serial_format register (r0x31ae) controls which serial format is in use when the serial interface is enabled (reset_register[1 2] = 0). the following serial formats are supported: ? 0x0304 - sensor supports quad-lane hispi operation ? 0x0302 - sensor supports dual-lane hispi operation pixel sensitivity figure 14: integration control in ers readout a pixel's integration time is defined by th e number of clock periods between a row's reset and read operation. both the read foll owed by the reset operations occur within a row period (t row ) where the read and reset may be a pplied to different rows. the read and reset operations will be applied to the ro ws of the pixel array in a consecutive order. the coarse integration time is defined by the number of row periods (t row ) between a row's reset and the row read. the row period is defined as the time between row read operations (see sensor frame rate). t coarse = t row * coarse_integration_time (eq 1) figure 15: example of 8.33m s integration in 16.6ms frame row integration (t integration ) row reset (start of integration) row readout vertical blanking read reset vertical blanking horizontal blanking t frame = frame_length_lines x t row 16.6 ms = 750 rows x 22.22 s/row t coarse = coarse_integration_time x t row 8.33 ms =563 rows x 22.22 s/row time
ar0141cs/d rev. 6, 4/16 en 17 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor pixel sensitivity figure 16: row read and row reset showing fine integration t fine = fine_integration_time/clk_pix (eq 2) the maximum allowed value for fine_integration_time is line_length_pck - fine_integ ration_time_ma x_margin (eq 3) figure 17: row integration time is greater than the frame readout time the minimum frame-time is defined by the number of row period s per frame and the row period. the sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines . read row n reset row k t fine = fine_integration _time x (1/clk_pix) start of read row n and reset row k start of read row n + 1 and reset row k + 1 t row = line_length _pck x (1/clk_pix) image vertical blanking vertical blanking shutter pointer read pointer time extended vertical blanking image 4.1 m s t frame = frame_length_lines x t row 16.6ms = 750 rows x 22.22 s/row t coarse =coarse_integration_time x t row 20.7ms = 930 rows x 22.22 s/row horizontal b lank ing horizontal b lank ing
ar0141cs/d rev. 6, 4/16 en 18 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor gain stages gain stages the sensor analog gain stage will apply the same analog gain to each color channel. digital gain can be configured to separate levels for each color channel. the level of analog gain applied is contro lled by the coarse_gain and fine_gain at r0x3060 analog gain register. the analog read out circuitry can be configured differently for each analog gain level. total analog gain is (2 coarse_gain ) x(1+fine_gain/16), where coarse_gain = r0x3060[6:4], fine_gain = r0x3060[3:0]. on semiconductor recommends limiting maximum analog gain up to 12x gain for optimal image quality. each digital gain can be configured from a gain of 0 to 15.992 using r0x3056, r0x3058, r0x305a, r0x305c, and r0x305e digital gain registers. the digital gain supports 128 gain steps per 6db of gain. the format of each di gital gain register is ?xxxx.yyyyyyy? where ?xxxx? refers an integer gain of 1 to 15 and ?yyyyyyy? is a fractional gain ranging from 0/ 128 to 127/128. the sensor includes a digital dithering feat ure to reduce quantiza tion noise resulting from using digital gain. it can be implemente d by setting r0x30ba[5] to 1. the default value is 0.
ar0141cs/d rev. 6, 4/16 en 19 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor data pedestals data pedestals the data pedestal is a constant offset that is added to pixel values at the end of the data- path. the default offset is 168 and is a 12- bit offset. this offset matches the maximum range used by the corrections in the digi tal readout path. the purpose of the data pedestal is to convert negative values gene rated by the digital datapath into positive output data. reset the ar0141cs may be reset by the reset_bar pin (active low) or the reset register. hard reset of logic the host system can reset the image sensor by bringing the reset_bar pin to a low state. alternatively, the reset_bar pin can be connected to an external rc circuit for simplicity. registers written via the two-wire interface will not be preserved following a hard reset. soft reset of logic soft reset of logic is controlled by the r0x 301a reset register. bit 0 is used to reset the digital logic of the sensor. furthermore, by a sserting the soft reset, the sensor aborts the current frame it is processing and starts a ne w frame. this bit is a self-resetting bit and also returns to ?0? during tw o-wire serial interface reads. clocks the ar0141cs requires one clock input (extclk). sensor pll vco figure 18: pll dividers affecting vco frequency the sensor contains a phase-locked loop (pll ) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre-pll clock divider followed by a multiplier. the pll multip lier should be an even integer. if an odd integer (m) is programmed, the pll will default to the lower (m-1) value to maintain an even multiplier value. the multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. extclk (6-50 mhz) pre_pll_clk_div 2 (1-64) pll_multiplier 58 (32-384) f vco
ar0141cs/d rev. 6, 4/16 en 20 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor sensor pll parallel pll configuration figure 19: pll for the parallel interface . the maximum output of the parallel interfac e is 74.25 mpixel/s. the sensor will not use the f serial , f serial_clk , or clk_op when configured to use the parallel interface. table 6: pll parameters for the parallel interface parameter symbol min max unit external clock extclk 6 50 mhz vco clock f vco 384 768 mhz output clock clk_op 74.25 mpixel/s table 7: example pll configuration for the parallel interface parameter value output f vco 445.5 mhz (max) vt_sys_clk_div 1 vt_pix_clk_div 6 clk_op 74.25 mpixel/s (= 445.5 mhz / 6) output pixel rate 74.25 mpixel/s f vco clk_op (max 74.25 mp/s) vt_pix_clk_div 6 (4-16) vt_sys_clk_div 1 (1, 2, 4, 6, 8, 10, 12, 14, 16) pre_pll_clk_div 2 (1-64) pll_multiplier 58 (32-384) extclk (6-50 mhz)
ar0141cs/d rev. 6, 4/16 en 21 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor sensor pll serial pll configuration figure 20: pll for the serial interface the sensor will use op_sys_clk_div and op_pix _clk_div to configure the output clock per lane (clk_op). the configuration will depend on the number of active lanes (1, 2, or 4) configured. to configure the sensor protocol and number of lanes, refer to ?serial configuration? on page 16. configure the serial output so that it adheres to the following rules: ? the maximum data-rate per lane (f serial ) is 600mbps/lane (hispi). ? configure the output pixel rate per lane (clk _op) so that the sensor output pixel rate matches the peak pixel rate (2 x clk_pix). ? 4-lane: 4 x clk_op = 2 x clk_pix = pixel rate (max: 148.5 mpixel/s) ? 2-lane: 2 x clk_op = 2 x clk_pix = pixel rate (max: 74.25 mpixel/s) table 8: pll parameters for the serial interface parameter symbol min max unit external clock extclk 6 50 mhz vco clock f vco 384 768 mhz readout clock clk_pix 74.25 mpixel/s output serial data rate per lane f serial 300 (hispi) 600 (hispi) mbps output serial clock speed per lane f serial_clk 150 (hispi) 350(hispi) mhz table 9: example pll configurat ions for the serial interface parameter 4-lane 2-lane units 12-bit 12-bit f vco 445.5 445.5 mhz vt_sys_clk_div 1 1 vt_pix_clk_div 6 12 op_sys_clk_div 1 1 f serial f vco f vco clk_pix clk_op extclk (6-50 mhz) f s e ria l_clk 1/2 pre_pll_clk_div 2 (1-64) vt_pix_clk_div 6 (4-16) vt_sys_clk_div 1 (1, 2, 4, 6, 8, 10, 12, 14, 16) pll_multiplier 58 (32-384) op_sys_clk_div (default = 1) op_pix_clk_div 12 (8, 10, 12, 14, 16)
ar0141cs/d rev. 6, 4/16 en 22 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor sensor pll stream/standby control the sensor supports a soft standby mode. in th is mode, the external clock can be option- ally disabled to further minimize power cons umption. if this is done, then the ?power- up sequence? on page 59 must be followed. soft standby soft standby is a low-power state that is controlled through register r0x301a[2]. depending on the value of r0x301a[4], the sens or will go to standb y after completion of the current frame readout. wh en the sensor comes back from soft standby, previously written register settings are still maintained. soft standby will not occur if the trigger pin is held high. a specific sequence needs to be followed to enter and exit from soft standby. entering soft standby: 1. set r0x301a[12] = 1 if serial mode was used 2. set r0x301a[2] = 0 and drive trigger pin low. 3. turn off external clock to fu rther minimize power consumption exiting soft standby: 1. enable external clock if it was turned off 2. set r0x301a[2] = 1 or drive trigger pin high. 3. set r0x301a[12] = 0 if serial mode is used op_pix_clk_div 12 12 f serial 445.5 445.5 mhz f serial_clk 222.75 222.75 mhz clk_pix 74.25 37.125 mpixel/s clk_op 37.125 37.125 mpixel/s pixel rate 148.5 74.25 mpixel/s table 9: example pll configurat ions for the serial interface parameter 4-lane 2-lane units 12-bit 12-bit
ar0141cs/d rev. 6, 4/16 en 23 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor sensor readout sensor readout image acquisition modes the ar0141cs supports two image acquisition modes: ? electronic rolling shutter (ers) mode this is the normal mode of operation. when the ar0141cs is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic wi thin the sensor sequences through the rows of the array, resetting and th en reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate inci- dent light. the integration (e xposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a unifor m integration time across the frame. when the integration time is changed (by using the two-wire serial interface to change regis- ter settings), the timing and control logic co ntrols the transition from old to new inte- gration time in such a way that the stre am of output frames from the ar0141cs switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?cha nges to integration time? in the ar0141cs register reference. ? global reset mode this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration time is controlled by an external electro- mechanical shutter, and the ar0141cs provid es control signals to interface to that shutter. the benefit of using an external electromechanic al shutter is that it eliminates the visual artifacts associated with ers operation. visu al artifacts arise in ers operation, particu- larly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is controll ed by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. readout modes horizontal mirror when the horiz_mirror bit (r0x3040[14]) is se t in the read_mode register, the order of pixel readout within a row is revers ed, so that readout starts from x_addr_end + 1 and ends at x_addr_start . figure 21 on page 24 shows a sequen ce of 6 pixels being read out with r0x3040[14] = 0 and r0x3040[14] = 1.
ar0141cs/d rev. 6, 4/16 en 24 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor sensor readout figure 21: effect of horizo ntal mirror on readout order vertical flip when the vert_flip bit (r0x3040[15]) is set in the read_mode register, the order in which pixel rows are read out is reversed , so that row readout starts from y_addr_end and ends at y_addr_start . figure 30 shows a sequence of 6 rows being read out with r0x3040[15] = 0 and r0x3040[15] = 1. figure 22: effect of vertical flip on readout order g0[11:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] g3[11:0] r2[11:0] g2[11:0] r1[11:0] g1[11:0] r0[11:0] line_valid horiz_mirror = 0 d out [11:0] horiz_mirror = 1 d out [11:0] row0[11:0] row1[11:0] row2[11:0] row3[11:0] row4[11:0] row5[11:0] row6[11:0] row5[11:0] row4[11:0] row3[11:0] row1[11:0] frame_valid vert_flip = 0 d out [11:0] vert_flip = 1 d out [11:0] row2[11:0]
ar0141cs/d rev. 6, 4/16 en 25 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor subsampling subsampling the ar0141cs supports subsampling. subsampl ing allows the sensor to read out a smaller set of active pixels by either ski pping, binning, or summing pixels within the readout window. figure 23: horizontal binning in the ar0141cs sensor horizontal binning is achieved either in the pixel readout or the digital readout. the sensor will sample the combined 2x adja cent pixels within the same color plane. figure 24: vertical row binning in the ar0141cs sensor vertical row binning is applied in the pixel re adout. row binning can be configured as 2x rows within the same color plane. pixel skipping can be co nfigured up to 2x in both the x-direction and y-direction. skip- ping pixels in the x-direction will not reduce the row time. sk ipping pixels in the y-direc- tion will reduce the number of rows from the sensor effectively reducing the frame time. skipping will introduce image artifacts from aliasing. the sensor increments its x and y address based on the x_odd_inc and y_odd_inc value. the value indicates the addresses that are skipped after each pair of pixels or rows has been read. table 10: available skip and bin modes in the ar0141cs sensor subsampling method horizontal vertical skipping 2x 2x binning 2x 2x lsb lsb lsb lsb - lsb lsb e - e - e - e -
ar0141cs/d rev. 6, 4/16 en 26 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor subsampling the sensor will increment x and y addresses in multiples of 2. this indicates that a greenr and red pixel pair will be read together. as well, that the sensor will read a gr-r row first followed by a b-gb row. (eq 4) (eq 5) a value of 1 is used for x_odd_inc and y_odd_inc when no pixel subsampling is indicated. in this case, the sensor is incrementing x and y addresses by 1 + 1 so that it reads consec- utive pixel and row pairs. to implement a 2x skip in the x direction, the x_odd _inc is set to 3 so that the x address increment is 1+3, meaning that sensor will skip every other gr- r pair. note: in skip2 the window size has to be a multiple of 4. table 11: configuration for horizontal subsampling x_odd_inc restrictions no subsampling x_odd_inc = 1 skip = (1+1)*0.5 = 1x the horizontal fov must be programmed to meet the following rule: skip 2x x_odd_inc = 3 skip = (1+3)*0.5 = 2x analog bin 2x x_odd_inc = 3 skip = (1+3)*0.5 =2x col_sf_bin_en = 1 digital bin 2x x_odd_inc = 3 skip = (1+3)*0.5 =2x col_bin =1 table 12: configuration fo r vertical subsampling y_odd_inc restrictions: no subsampling y_odd_inc = 1 skip = (1+1)*0.5 = 1x row_bin = 0 the vertical fov must be programmed to meet the following rule: skip 2x y_odd_inc = 3 skip = (1+3)*0.5 =2x row_bin = 0 analog bin 2x y_odd_inc = 3 skip = (1+3)*0.5 =2x row_bin = 1 x subsampling factor 1 x_odd_inc + 2 ------------------ ---------------- - = y subsampling factor 1 y_odd_inc + 2 ------------------ ---------------- - = x_addr_end x_addr_start ?1 + x_odd_inc 1 + ?? 2 ? ------------------------------------------------------------------------- e v e n n u m b e r = y _addr_end y _addr_start ?1 + y _odd_inc 1 + ?? 2 ? ------------------------------------------------------------------------- e v e n n u m b e r =
ar0141cs/d rev. 6, 4/16 en 27 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor sensor frame rate sensor frame rate the time required to re ad out an image frame (t frame ) can be derived from the number of clocks required to output each image and the pixel clock. the frame-rate is the inverse of the frame period. fps=1/t frame (eq 6) the number of clocks can be simplified further into the following parameters: ? the number of clocks required for each sensor row ( line_length_pck ) this parameter also determines the sensor row period when refere nced to the sensor readout clock. (t row = line_length_pck x 1/clk_pix) ? the number of row periods per frame ( frame_length_lines ) ? an extra delay between frames used to achieve a specific output frame period ( extra_delay ) t frame =1/(clk_pix) [frame_leng th_lines line_length_pck + extra_delay] (eq 7) figure 25: frame period measured in clocks frame_length_lines = active rows + vb
ar0141cs/d rev. 6, 4/16 en 28 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor slave mode row period (t row ) line_length_pck will determine the number of cloc k periods per row an d the row period (t row ) when combined with the sensor readout clock. line_length_pck includes both the active pixels and the horizontal blanking time per row. the sensor utilizes two readout paths, as seen in figure 1 on page 4, allowing the sensor to output two pixels during each pixel clock. row periods per frame frame_length_lines determines the number of row periods (t row ) per frame. this includes both the active and blanking rows . the minimum vertical blanking value is defined by the number of ob rows read per frame, two embedded data rows, and two blank rows. (eq 8) the sensor is configured to output frame information in two embedded data rows by setting r0x3064[8] to 1 (default). if r0x3064[8] is set to 0, the sensor will instead output two blank rows. the data configured in the two embedded rows is defined in two embedded rows of data at the top of the fr ame by setting r0x3064[7] and two rows of embedded statistics at the en d of the frame by setting r0 x3064[7] for exposure calcula- tions. see the section on em bedded data and statistics. the locations of the ob rows, embedded rows , and blank rows within the frame readout are identified in figure 26: ?slave mode acti ve state and vertical blanking,? on page 29. slave mode the slave mode feature of the ar0141cs suppor ts triggering the star t of a frame readout from a vd signal that is supp lied from an external device. the slave mode signal allows for precise control of frame rate and register change updates. the vd signal is an edge triggered input to the trigger pin and must be at least 3 pixclk cycles wide. table 13: minimum vertical blanking configuration r0x3180[7:4] ob rows min_vertical_blanking 1 0x8 (default) 8 ob rows 8 ob + 8 = 16 0x4 4 ob rows 4 ob + 8 = 12 0x2 2 ob rows 2 ob + 8 = 10 minimum frame_length_lines y_addr_end y_addr_start ?1 + y_odd_inc 1 + ?? 2 ? -------------------- --------------------- ----------------- ----------------- min_vertical_blanking + =
ar0141cs/d rev. 6, 4/16 en 29 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor slave mode figure 26: slave mode active state and vert ical blanking if the slave mode is disabled, the new frame will begin after the extra delay period is finished. the slave mode will react to the rising edge of the input vd signal if it is in an active state. when the vd signal is received, the sensor will begin the frame readout and the slave mode will remain inactive for the period of one frame time plus 16 clock periods (t frame + (16 / clk_pix)). after this period, the slave mode will re-enter the active state and will respond to the vd signal. start of frame n end of frame n start of frame n + 1 time frame valid ob rows (2, 4, or 8 rows) embedded data row (2 rows) active data rows blank rows or embedded stats (2 rows) extra vertical blanking (frame_length_lines - min_frame_length_lines) vd signal slave mode active state the period between the rising edge of the vd signal and the slave mode ready state is t frame + 16 clocks. extra delay (clocks)
ar0141cs/d rev. 6, 4/16 en 30 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor slave mode figure 27: slave mode example with eq ual integration and frame readout periods the integration of the last row is started before th e end of the programmed integration for the first row. the row shutter and read operations will st op when the slave mode becomes active and is waiting for the vd signal. the following should be considered when configuring the sensor to use the slave mode: 1. the frame period (t frame ) should be configured to be less than the period of the input vd signal. the sensor will disregard th e input vd signal if it appears before the frame readout is finished. 2. if the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input vd signal. this error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between vd signals). inactive active row 0 row n inactive active rising edge rising edge row readout programmed integration integration due to slave mode delay slave mode trigger rising edge of vd signal triggers the start of the frame readout. row reset (start of integration) frame valid vd signal rising edge the slave mode will become active after the last row period. both the row reset and row read operations will wait until the rising edge of the vd signal.. row reset and read operations begin after the rising edge of the vd signal.
ar0141cs/d rev. 6, 4/16 en 31 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor slave mode figure 28: slave mode example where the integrat ion period is half of the frame readout period the sensor read pointer will have paused at row 0 while th e shutter pointer pauses at ro w n/2. the extra integration caused by the slave mode delay will only be seen by rows 0 to n/2. the example below is for a frame readout period of 16.6ms while the integration time is configured to 8.33ms. when the slave mode becomes active, the sens or will pause both row read and row reset operations. (note: the row inte gration period is defined as the period from row reset to row read.) the frame-time should therefore be configured so that the slave mode ?wait period? is as short as possible. in the case where the sensor integration time is shorter than the frame time, the ?wait period? will only increase the integration of the rows that have been reset following the last vd pulse. the period between slave mode pulses must also be greater than the frame period. if the rising edge of the vd pulse arrives while the slave mode is inactive, the vd pulse will be ignored and will wait until the next vd pulse has arrived. to enter slave mode: 1. while in soft-standby, set r0x30ce[4] = 1 to enter slave mode. 2. enable the input pins (trigge r) by setting r0x301a[8] = 1. 3. enable streaming by setting r0x301a[2] = 1. 4. apply sync-pulses to the trigger input. inactive active row 0 row n inactive active rising edge rising edge row readout programmed integration integration due to slave mode delay slave mode trigger row reset (start of integration) frame valid vd signal rising edge reset operation is held during slave mode active state. row reset and read operations begin after the rising edge of the vd signal. 8.33 ms 8.33 ms
ar0141cs/d rev. 6, 4/16 en 32 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor frame readout frame readout the sensor readout begins with vertical blanking rows followed by the active rows. the frame readout period can be defined by the number of row periods within a frame ( frame_length_lines ) and the row period ( line_length_pck/clk_pix ). the sensor will read the first vertical blanking row at the beginning of the frame period and the last active row at the end of the row period. figure 29: example of the sensor output of a 1280 x 720 frame at 60 fps the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming-sp protocol. figure 29 aligns the frame integration and read out operation to the sensor output. it also shows the sensor output using the hispi stre aming-sp protocol. di fferent sensor proto- cols will list different sync codes. active rows vertical blanking time 1/60s end of frame readout end of frame readout start of vertical blanking start of frame start of active row end of line serial sync codes end of frame row reset row read row reset row read frame valid line valid 1/60s row reset row read row reset row read 1280 x 720 1280 x 720 hb (370 pixels/column) hb (370 pixels/column) vb (30 rows) vb (30 rows)
ar0141cs/d rev. 6, 4/16 en 33 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor frame readout figure 30 illustrates how the sensor acti ve readout time can be minimized while reducing the frame rate. 750 vb rows were added to the output frame to reduce the 1280 x 720 frame rate from 60 fps to 30 fps without increasing the delay between the readout of the first and last active row. figure 30: example of the sensor output of a 1280 x720 frame at 30 fps the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming-sp protocol. table 14: serial sync codes included with each protocol included with the ar0141cs sensor interface/protocol start of vertical blanking row (sov) start of frame (sof) start of active line (sol) end of line (eol) end of frame (eof) parallel parallel interface uses frame va lid (fv) and line valid (lv) outputs to denote start and end of line and frame. hispi streaming-s required unsupport ed required unsupported unsupported hispi streaming-sp required required required unsupported unsupported hispi packetized sp unsupported required required required required serial sync codes vb (780 rows) h b (370 p ixels ) h b (370 p ixels ) frame valid line valid 1/30s 1/30s active rows vertical blanking time end of frame readout start of vertical blanking start of frame start of active row end of line end of frame row reset row read row reset row read 1280 x 720 1280 x 720 row reset row read row reset row read end of frame readout vb (780 rows)
ar0141cs/d rev. 6, 4/16 en 34 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor changing sensor modes changing sensor modes register changes all register writes are delayed by one frame. a register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2 . this includes writes to the sensor gain and integration registers. real-time context switching in the ar0141cs, the user may switch between two full register sets a and b by writing to a context switch change bit in r0x30b0[13]. when the context switch is configured to context a the sensor will reference the cont ext a registers. if the context switch is changed from a to b during the readout of frame n , the sensor will then reference the context b coarse_integration_time registers in frame n+1 and all other context b registers at the beginning of reading frame n+2 . the sensor will show the same behavior when changing from context b to context a. table 15: list of configurable registers for context a and context b context a context b register description address register description address coarse_integration_time 0x3012 coarse_integration_time_cb 0x3016 line_length_pck 0x300c line_length_pck_cb 0x303e frame_length_lines 0x300a frame_length_lines_cb 0x30aa row_bin 0x3040[12] row_bin_cb 0x3040[10] col_bin 0x3040[13] col_bin_cb 0x3040[11] fine_gain 0x3060[3:0] fine_gain_cb 0x3060[11:8] coarse_gain 0x3060[5:4] coarse_gain_cb 0x3060[13:12] x_addr_start 0x3004 x_addr_start_cb 0x308a y_addr_start 0x3002 y_addr_start_cb 0x308c x_addr_end 0x3008 x_addr_end_cb 0x308e y_addr_end 0x3006 y_addr_end_cb 0x3090 y_odd_inc 0x30a6 y_odd_inc_cb 0x30a8 x_odd_inc 0x30a2 x_odd_inc_cb 0x30ae green1_gain 0x3056 green1_gain_cb 0x30bc blue_gain 0x3058 blue_gain_cb 0x30be red_gain 0x305a red_gain_cb 0x30c0 green2_gain 0x305c green2_gain_cb 0x30c2 global_gain 0x305e global_gain_cb 0x30c4
ar0141cs/d rev. 6, 4/16 en 35 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor changing sensor modes figure 31: example of changing th e sensor from context a to context b compression the ar0141cs can optionally compress 12-bit data to 10-bit using a-law compression. the compression is applied after the data pede stal has been added to the data. see ?data pedestals? on page 19. the a-law compression is disabled by default and can be enabled by setting r0x31d0 from ?0? to ?1? and 0x31ac needs to be set to 0x0c0a. table 16: a-law compression table for 12-10 bits input range input values compressed codeword 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g 128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g 256 to 511 0 0 0 1 a b c d e f g x 0 1 0 a b c d e f g 512 to 1023 0 0 1 a b c d e f g x x 0 1 1 a b c d e f g 1024 to 2047 0 1 a b c d e f g h x x 1 0 a b c d e f g h 2048 to 4095 1 a b c d e f g h x x x 1 1 a b c d e f g h active rows vertical blanking time 1/60s 1/60s start of vertical blanking start of frame start of active row end of frame serial sync codes c end of frame readout end of frame readout end of frame readout 1/30s 1280 x720 frame n+1 1 280 x 720 frame n vb (30 r ows) h b (370 p ixels/c olum n) vb (30 r ows) h b (370 p ixels/c olum n) 1280 x 720 frame n+2 vb (780 rows) h b (370 p ixels/c olum n) write context a to b during readout of frame n integration time of context b mode implemented during readout of frame n+1 context b mode is implemented in frame n+2
ar0141cs/d rev. 6, 4/16 en 36 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor changing sensor modes temperature sensor the ar0141cs sensor has a built-in temperat ure sensor, accessible through registers, that is capable of measuring die junction temperature. the temperature sensor can be enabled by writing r0x30b4[0]=1 and r0x30b4[4]=1. after this, the temperature sensor output value can be read from r0x30b2[9:0]. the value read out from the temperature sens or register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius. since the ptat device characteristic response is qu ite linear in the temperature range of oper- ation required, a simple linear function in th e format of the equation below can be used to convert the adc output value to the final temperature in degrees celsius. (eq 9) for this conversion, a minimum of two known points are needed to construct the line formula by identifying the slope and y-intercept ?t 0 ?. these calibration values can be read from registers r0x30c6 and r0x30c 8, which correspond to value read at 105 c and 55 c respectively. once read, the slope and y-intercept values can be calculated and used in equation 9. for more information on the temperature sensor registers, refer to the ar0141cs register reference. temperature slope r0x30b2 9:0 ?? t + ? 0 =
ar0141cs/d rev. 6, 4/16 en 37 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor changing sensor modes embedded data and statistics the ar0141cs has the capability to output image data and statistics embedded within the frame timing. there are two types of information embedded within the frame readout. ? embedded data: if enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. ?embedded statistics: if enabled, these are displayed on the two ro ws immediately after the last active pixel row is displayed. figure 32: frame format with embedded data lines enabled embedded data the embedded data contains the configurat ion of the image being displayed. this includes all register settings used to capt ure the current frame. the registers embedded in these rows are as follows: line 1: registers r0x3000 to r0x312f line 2: registers r0x3136 to r0x31bf, r0x31d0 to r0x31ff note: all undefined registers will have a value of 0. in parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where th e register data will be broken up into 8 msb and 8 lsb. the alignment of the 8-bit data will be on the 8 msb bits of the 12-bit pixel word. for example, if a register value of 0x1234 is to be transmitted, it will be transmitted over two, 12-bit pixels as follows: 0x120, 0x340. embedded statistics the embedded statistics contain frame iden tifiers and histogram information of the image in the frame. this can be used by do wnstream auto-exposure algorithm blocks to make decisions about exposure adjustment. image register data status & statistics data hblank vblank
ar0141cs/d rev. 6, 4/16 en 38 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor changing sensor modes this histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 2 8 , 120 evenly spaced bins for values 2 8 to 2 12 , 60 evenly spaced bins for values 2 12 to 2 16 . it is recommended that auto ex posure algorithms be developed using the histogram statistics on line 1. the first pixel of each line in the embedded statistics is a tag value of 0x0b0. this signi- fies that all subsequent statistics data is 10 bit data aligned to the msb of the 12-bit pixel. figure 33 summarizes how the embedded statistics transmission looks like. it should be noted that data, as shown in figure 33, is aligned to the msb of each word: figure 33: format of embedded statistics output within a frame the statistics embedded in these rows are as follows: line 1: ? 0x0b0 - identifier ? register 0x303a - frame_count ? register 0x31d2 - frame id ? histogram data - histogram bins 0-243 line 2: ? 0x0b0 (tag) ?mean ? histogram begin ?histogram end ?low end histogram mean ? percentage of pixels below low end mean ? normal absolute deviation {2'b00,frame _count msb} {2'b00,frame _count lsb} {2'b00,frame _id msb} {2'b00,frame _id lsb} histogram bin0 [19:10] histogram bin0 [9:0] histogram bin1 [19:0] histogram bin1 [9:0] # words = 10'h1ec data_format_ code = 8'h0b histogram bin243 [19:0] histogram bin243 [9:0] # words = 10'h00c data_format_ code = 8'h0b mean [19:10] mean [9:0] histbegin [19:10] histbegin [9:0] histend [19:10] histend [9:0] lowendmean [19:10] lowendmean [9:0] perc_lowend [19:10] perc_lowend [9:0] norm_abs_ dev [19:10] norm_abs_ dev [9:0] 8'h07 8'h07 8'h07 stats line 1 stats line 2
ar0141cs/d rev. 6, 4/16 en 39 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor changing sensor modes test patterns the ar0141cs has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are selected by test_pattern_mode register (r 0x3070). only one of the test patterns can be enabled at a given point in time by setting the test_pattern_mode register according to table 17. when test patterns are enabled th e active area will receive the value speci- fied by the selected test pattern and the dark pixels will receive the value in test_pat- tern_green (r0x3074 and r0x3078) for green pixels, test_pattern_blue (r0x3076) for blue pixels, and test_pattern_red (r0x3072) fo r red pixels. the noise pedestal offset at register 0x30fe impacts on the test pattern ou tput, so the noise_pedestal needs to be set as 0x0000 for normal test pattern output. solid color when the color field mode is selected, the valu e for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when the vertical color bars mode is select ed, a typical color bar pattern will be sent through the digital pipeline. walking 1s when the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. the first value in each row is 1. table 17: test pattern modes test_pattern_mode test pattern output 0 no test pattern (normal operation) 1 solid color test pattern 2 100% vertical color bars test pattern 3 fade-to-gray vertical co lor bars test pattern 256 walking 1s test pattern (12-bit)
ar0141cs/d rev. 6, 4/16 en 40 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read/write access to control and status regis- ters within the ar0141cs.the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in th e two-wire serial interface specification allow the slave device to drive s clk low; the ar0141cs uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start an d stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can ge nerate a start conditio n without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high.
ar0141cs/d rev. 6, 4/16 en 41 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor two-wire serial register interface slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indica tes a write, and a ?1? indicates a read. the default slave addresses used by the ar0141cs are 0x20 (write address) and 0x21 (read address) in accordance with the specification. alternate sl ave addresses of0x30 (write address) and0x31 (read address) can be se lected by enabling and asserting the s addr input. an alternate slave address can also be programmed through r0x31fc. message byte message bytes are used for sending register ad dresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receip t of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s intern al register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0141cs/d rev. 6, 4/16 en 42 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor two-wire serial register interface single read from random location this sequence (figure 34) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 34 shows how the internal register address maintained by the ar0141cs is loaded and incremented as the sequence proceeds. figure 34: single read from random location single read from current location this sequence (figure 35) performs a read using the current value of the ar0141cs internal register address. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 35: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a
ar0141cs/d rev. 6, 4/16 en 43 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 36) starts in the same way as the single read from random loca- tion (figure 34). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 36: sequential read, start from random location sequential read, start from current location this sequence (figure 37) starts in the same way as the single read from current loca- tion (figure 35). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 37: sequential read, start from current location single write to random location this sequence (figure 38) begins with the master generating a start condition. the slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 38: single write to random location slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+ 1 a a write data
ar0141cs/d rev. 6, 4/16 en 44 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor two-wire serial register interface sequential write, sta rt at random location this sequence (figure 39) starts in the same way as the single write to random location (figure 38). instead of generating a no-acknowl edge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 39: sequential write, start at random location slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
ar0141cs/d rev. 6, 4/16 en 45 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor spectral characteristics spectral characteristics figure 40 specifies the quantum efficiency of the rgb bayer sensor. figure 40: quantum efficiency - color sensor
ar0141cs/d rev. 6, 4/16 en 46 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor spectral characteristics figure 41 specifies the quantum effi ciency of the monochrome sensor. figure 41: quantum efficiency - monochrome sensor
ar0141cs/d rev. 6, 4/16 en 47 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor spectral characteristics figure 42: rgb-ni r quantum efficiency 0 10 20 30 40 50 60 70 350 450 550 650 750 850 950 1050 1150 quantum efficiency (%) wavelength (nm) blue green nir red
ar0141cs/d rev. 6, 4/16 en 48 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor spectral characteristics figure 43: chief ray angle - 21deg image height cra (%) (mm) (deg) 00 0 5 0.113 1.01 10 0.226 2.03 15 0.340 3.07 20 0.453 4.11 25 0.566 5.17 30 0.679 6.23 35 0.792 7.30 40 0.906 8.38 45 1.019 9.46 50 1.132 10.54 55 1.245 11.63 60 1.358 12.73 65 1.472 13.82 70 1.585 14.92 75 1.698 16.01 80 1.811 17.10 85 1.925 18.19 90 2.038 19.28 95 2.151 20.36 100 2.264 21.43 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100 110 cra (deg) image height (%) ar0141 mono cra characteristic
ar0141cs/d rev. 6, 4/16 en 49 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications electrical specifications unless otherwise stated, the following specifications apply under the following condi- tions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = -30 c to +85 c; output load = 10pf; frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characterist ics of the two-wire serial register interface (s clk , s data ) are shown in figure 44 and table 18. figure 44: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read wa veforms start after write command and register address are issued. table 18: two-wire seri al bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard mode fast mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line c b - 400 - 400 pf s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
ar0141cs/d rev. 6, 4/16 en 50 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications notes: 1. this table is based on i 2 c standard (v2.1 january 20 00). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a ho ld time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must th en be met. this will automatically be th e case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specificatio n) before the s clk line is released. 7. c b = total capacitance of one bus line in pf. i/o timing by default, the ar0141cs launches pixel data, fv, and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the rising edge of pixclk. see figure 45 for i/o timing diagram. figure 45: i/o timing diagram serial interface input pin capacitance c in_si - 3.3 - 3.3 pf s data max load capacitance c load_sd -30-30pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ? table 18: two-wire serial bu s characteristics (continued) f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard mode fast mode unit min max min max data[11:0] line_valid/ pixclk extclk t r t extclk t f frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. t plh t pfh t pfl t pll t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% t rp t fp 90% 10% frame_valid
ar0141cs/d rev. 6, 4/16 en 51 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications note: slew rate setting = 2 for pixclk slew rate setting = 2 for parallel ports table 19: i/o timing characteristics (2.8v v dd _io) conditions: f pixclk =37.125 mhz (720p30fps; v dd _io = 2.8v symbol definition condition min typ max unit f extclk1 input clock frequency pll enabled 6 C 50 mhz t extclk1 input clock period pll enabled 20 C 166 ns t r input clock rise time C 3 C ns t f input clock fall time C 3 C ns t rr pixclk rise time pclk slew rate setting= 2 2.0 3.5 6.4 ns t fp pixclk fall time pclk slew rate setting= 2 1.9 3.3 6.2 ns clock duty cycle 45 50 55 % t jitter2 input clock jitter at 27 mhz C C 600 ps f pixclk pixclk frequency default pll configuration 6 37.125 74.25 mhz t pd pixclk to data[11:0] pclk slew rate setting=2 parallel slew rate setting= 4 -2.0 C 5.9 ns t pfh pixclk to fv high pclk slew rate setting=2 parallel slew rate setting=2 -0.9 C 4.4 ns t plh pixclk to lv high pclk slew rate setting=2 parallel slew rate setting=2 -0.8 C 4.6 ns t pfl pixclk to fv low pclk slew rate setting=2 parallel slew rate setting=2 -1.5 C 3.1 ns t pll pixclk to fv low pclk slew rate setting=2 parallel slew rate setting=2 -1.5 C 3.3 ns c load output load capacitance C 30 C pf c in input pin capacitance C 2.5 C pf
ar0141cs/d rev. 6, 4/16 en 52 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications note: slew rate setting = 2 for pixclk slew rate setting = 2 for parallel ports note: 30pf loads at nominal voltages. table 20: i/o timing ch aracteristics (1.8v v dd _io) conditions: f pixclk = 37.125 mhz(720p30fps;) v dd _io = 1.8v symbol definition c condition min typ max unit f extclk1 input clock frequency pll enabled 6 C 50 mhz t extclk1 input clock period pll enabled 20 C 166.6666667 ns t r input clock rise time C 3 C ns t f input clock fall time C 3 C ns t rr pixclk rise time pclk slew rate setting=2 3.2 5.6 9.5 ns t fp pixclk fall time pclk slew rate setting=2 2.9 5.0 8.8 ns clock duty cycle 45 50 55 % t jitter2 input clock jitter at 27 mhz C C 600 ps f pixclk pixclk frequency default pll configuration 6 37.125 74.25 mhz t pd pixclk to data[11:0] pclk slew rate setting=2 parallel slew rate setting=2 -2.2 C 5.9 ns t pfh pixclk to fv high pclk slew rate setting=2 parallel slew rate setting=2 -0.9 C 4.5 ns t plh pixclk to lv high pclk slew rate setting=2 parallel slew rate setting=2 -0.9 C 4.6 ns t pfl pixclk to fv low pclk slew rate setting=2 parallel slew rate setting=2 -1.7 C 3.1 ns t pll pixclk to fv low pclk slew rate setting=2 parallel slew rate setting=2 -1.6 C 3.4 ns c load output load capacitance C 30 C pf c in input pin capacitance C 2.5 C pf table 21: i/o rise slew rate (2.8v v dd _io) parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.83 1.38 2.1 v/ns 6 default 0.71 1.2 1.84 v/ns 5 default 0.64 1.07 1.65 v/ns 4 default 0.56 0.94 1.44 v/ns 3 default 0.47 0.79 1.21 v/ns 2 default 0.39 0.64 0.98 v/ns 1 default 0.29 0.48 0.74 v/ns 0 default 0.2 0.32 0.49 v/ns
ar0141cs/d rev. 6, 4/16 en 53 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications note: 30pf loads at nominal voltages. note: 30pf loads at nominal voltages. note: 30pf loads at nominal voltages. table 22: i/o fall slew rate (2.8v v dd _io) parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.76 1.25 1.85 v/ns 6 default 0.67 1.12 1.68 v/ns 5 default 0.61 1.04 1.56 v/ns 4 default 0.55 0.93 1.41 v/ns 3 default 0.48 0.81 1.23 v/ns 2 default 0.4 0.67 1.03 v/ns 1 default 0.31 0.52 0.79 v/ns 0 default 0.21 0.35 0.54 v/ns table 23: i/o rise slew rate (1.8v v dd _io) parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.32 0.51 0.85 v/ns 6 default 0.28 0.44 0.75 v/ns 5 default 0.25 0.4 0.68 v/ns 4 default 0.23 0.36 0.6 v/ns 3 default 0.2 0.31 0.51 v/ns 2 default 0.17 0.26 0.41 v/ns 1 default 0.13 0.2 0.32 v/ns 0 default 0.09 0.13 0.21 v/ns table 24: i/o fall slew rate (1.8v v dd _io) parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.32 0.53 0.87 v/ns 6 default 0.28 0.47 0.77 v/ns 5 default 0.26 0.43 0.71 v/ns 4 default 0.24 0.39 0.64 v/ns 3 default 0.21 0.34 0.56 v/ns 2 default 0.18 0.29 0.47 v/ns 1 default 0.14 0.22 0.36 v/ns 0 default 0.1 0.16 0.25 v/ns
ar0141cs/d rev. 6, 4/16 en 54 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications dc electrical characteristics the dc electrical characteristics are shown in the tables below. caution stresses greater than those listed in table 26 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. note: exposure to ab solute maximum rating conditions for extended periods may affect reliability. table 25: dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _io*0.7 C C v v il input low voltage C C v dd _io*0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 20 C C ? a v oh output high voltage v dd _io-0.3 C C v v ol output low voltage C C 0.4 v i oh output high current at specified v oh -22 C C ma i ol output low current at specified v ol CC22ma table 26: absolute maximum ratings symbol definition condition min max unit v dd _max core digital voltage C0.3 2.4 v v dd _io_max i/o digital voltage C0.3 4 v v aa _max analog voltage C0.3 4 v v aa _pix pixel supply voltage C0.3 4 v v dd _pll pll supply voltage C0.3 4 v vdd_slvs_max hispi i/o digital voltage C0.3 2.4 v t st storage temperature C40 150 c
ar0141cs/d rev. 6, 4/16 en 55 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications note: operating currents are measure d at the following conditions: v aa = v aa _pix = v dd _pll = 2.8v v dd = v dd _io = 1.8v; c load = 68pf pll enabled and pixclk = 74.25 mhz 1x analog gain, 0.36 ms integratio n time, 60 fps, dark conditions t j = 25 c note: v aa = v aa _pix = v dd _pll = 2.8v v dd = v dd _io = 1.8v v dd _slvs=1.8v for hivcm and =0.4v for slvs pll enabled and pixclk = 74.25 mhz 1x analog gain, 0.36 ms integratio n time, 60 fps, dark conditions t j = 25c notes: 1. analog = v aa + v aa _pix + v dd _pll 2. digital = v dd _io + v dd _slvs table 27: operating current consumption in parallel output and linear mode definition condition symbol min typ max unit digital operating current streaming,1280x720 60 fps i dd 1 C 137 160 ma i/o digital operating current streaming,1280x720 60 fps i dd _io C 15 25 ma analog operating current stre aming,1280x720 60 fps i aa C2030ma pixel supply current streaming,1280x720 60 fps i aa _pix C 1.5 3 ma pll supply current streaming,1280x720 60 fps i dd _pll C 4 8 ma table 28: operating currents in hispi output and linear mode definition condition symbol min typ max unit digital operating current streaming,1280x720 60 fps i dd C147 170 ma analog operating current streaming,1280x720 60 fps i aa C20 30 ma pixel supply current streaming,1280x720 60 fps i aa _pix C 1.5 3 ma pll supply current stream ing,1280x720 60 fps i dd _pll C 5 9 ma slvs supply current streaming,1280x720 60 fps i dd _slvs C 8 15 ma hivcm supply current streaming,1280x720 60 fps i dd C22 25 ma table 29: standby current consumption definition condition symbol min typ max unit soft standby (clock off) analog, 2.8v - C 0 0.1 ma digital, 1.8v - C 0.1 0.25 ma soft standby (clock on) analog, 2.8v - C 0.01 0.2 ma digital, 1.8v - C 26 30 ma
ar0141cs/d rev. 6, 4/16 en 56 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications hispi electrical specifications note: refer to ?high-speed serial pixel interface physical layer specification v2.00.00? for further explanation of the hispi transmitte r specification. the electrical specifica- tions below supersede those given in the hispi physical layer specification. notes: 1. temperature of 25c 2. up to 600 mbps table 30: slvs power supply and operating temperature parameter symbol min typ max unit slvs current consumption 1, 2 i dd _tx 18 ma hispi phy current consumption 1,2 i dd _hispi 45 ma operating temperature 3 t a -30 70 c table 31: slvs electrical dc specification parameter symbol min typ max unit slvs dc mean common mode voltage v cm 0.45*v dd _ tx 0.5*v dd _ tx 0.55*v dd _ tx v slvs dc mean differential output voltage |v od |0.36*v dd _ tx 0.5*v dd _ tx 0.64*v dd _ tx v change in v cm between logic 1 and 0 ? v cm 25 mv change in |v od | between logic 1 and 0 |v od |25mv v od noise margin nm 30 % difference in v cm between any two channels | ? v cm |50mv difference in v od between any two channels | ? v od |100mv common-mode ac voltage (pk) without v cm cap termination v cm _ ac 50 mv common-mode ac voltage (pk) with v cm cap termination v cm _ ac 30 mv maximum overshoot peak |v od | v od _ ac 1.3*|v od |v maximum overshoot vdiff pk-pk v diff_pkpk 2.6*v od v single-ended output impedance r o 35 50 70 ? output impedance mismatch ? r o 20 %
ar0141cs/d rev. 6, 4/16 en 57 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from the 0v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew betw een complementary outputs. it is measured as the absolute time between the two complementary edge s at mean vcm point. no te that differential skew also is related to the ? v cm _ ac spec, which also must not be exceeded. figure 46: differential output voltage for clock or data pairs table 32: slvs electrical timing specification parameter symbol min max unit notes data rate 1/ui 280 600 mbps 1 bitrate period t pw 1.43 3.57 ns 1 max setup time from transmitter t pre 0.3 ui 1, 2 max hold time from transmitter t post 0.3 ui 1, 2 eye width t eye 0.6 ui 1, 2 data total jitter (pk-pk) @1e-9 t totaljit 0.2 ui 1, 2 clock period jitter (rms) t ckjit 50 ps 2 clock cycle-to-cycle jitter (rms) t cycjit 100 ps 2 rise time (20% - 80%) t r 150ps 0.25 ui 3 fall time (20% - 80%) t f 150ps 0.25 ui 3 clock duty cycle d cyc 45 55 % 2 mean clock to data skew t chskew -0.1 0.1 ui 1, 4 phy-to-phy skew t physkew 2.1 ui 1, 5 mean differential skew t diffskew -100 100 ps 6 0v diff) vdiffmax vdiffmin output signal is 'cp - cn' or 'dp - dn'
ar0141cs/d rev. 6, 4/16 en 58 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications figure 47: eye diagram for clock and data signals figure 48: hispi skew between data signals within the phy table 33: channel, phy, and intra-phy skew measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.8v; data rate =480 mbps; dll set to 0 data lane skew in reference to clock tchskew1phy -150 ps clkjitter t rigger/ reference vdiff max vdiff ui/ 2 ui/ 2 vdiff txpre txpost clock mask data mask rise fall 20% 80% tc hskew1phy
ar0141cs/d rev. 6, 4/16 en 59 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications note: the clock dll steps 6 and 7 are not recomm ended by on semiconductor for the ar0141cs. note: the data dll steps 3, 5, and 7 are not re commended by on semico nductor for the ar0141cs. power-up sequence the recommended power-up sequence for the ar0141cs is shown in figure 49. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 100 ? s, turn on v aa and v aa _pix power supply. 3. after 100 ? s, turn on v dd _io power supply. 4. after 100 ? s, turn on vdd power supply. 5. after 100 ? s, turn on vdd_slvs power supply. 6. after the last power supply is stable, enable extclk. 7. assert reset_bar for at least 1ms. the parall el interface will be tri-stated during this time. 8. wait 1800 extclks for internal initialization into software standby. 9. initiate load of otpm data by setting r0x304a=0x0010. 10. wait for 185135 extclks for a full otpm loading. 11. configure pll, output, and im age settings to desired values. 12. wait 1ms for the pll to lock. 13. set streaming mode (r0x301a[2] = 1). table 34: clock dll steps measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.8v; data dll set to 0 clock dll step 1 2 3 4 5 step delay at 660 mbps 0.25 0.375 0.5 0.625 0.75 ui eye_opening at 660 mbps 0.85 0.78 0.71 0.71 0.69 ui table 35: data dll steps measurement conditions: v dd _hispi = 1.8v;v dd _hispi_tx = 0.8v; clock dll set to 0 data dll step 1 2 4 6 step delay at 660 mbps 0.25 0.375 0.625 0.875 ui eye opening at 660 mbps 0.79 0.84 0.71 0.61 ui
ar0141cs/d rev. 6, 4/16 en 60 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications figure 49: power up notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required af ter power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality is sues and will experience high current draw on this supply. table 36: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix 3 t0 0 100 C ? s v aa /v aa _pix to v dd _io t1 0 100 C ? s v dd _io to v dd t2 0 100 C ? s v dd to v dd _slvs t3 0 100 C ? s xtal settle time tx C 30 1 Cms hard reset t4 1 2 CC ms internal initialization t5 1800 C C extclk otpm loading t6 185135 C C extclk pll lock time t7 1 C C ms v dd _p ll (2.8) v aa _p ix v aa (2.8) t0 v dd _io(1.8/2.8) t1 v dd (1.8) v dd _s lv s (0.4) t2 t3 extclk reset_bar t4 tx hard reset internal initialization software standby r0x304 a =0x0 0 1 0 otpm loading initialization s etting loading streaming pll lock t5 t6 t7
ar0141cs/d rev. 6, 4/16 en 61 ?semiconductor components industries, llc, 2016 ar0141cs: 1/4-inch digital image sensor electrical specifications power-down sequence the recommended power-down sequence for the ar0141cs is shown in figure 50. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depe nding on configuration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 50: power down v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle
ar0141cs/d rev. 6, 4/16 en 62 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor electrical specifications note: t4 is required between power down and next po wer up time; all decoupling caps from regulators must be completely discharged. table 37: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 C C ? s v dd to v dd _io t1 0 C C ? s v dd _io to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s pwrdn until next pwrup time t4 100 C C ms
ar0141cs/d rev. 6, 4/16 en 63 ?semiconductor components industries, llc, 2016. ar0141cs: 1/4-inch digital image sensor package drawings package drawings figure 51: 63-ball ibga package (case 503ah) notes: 1. dimensions are in mm. dime nsions in () are for reference only. 2. encapsulant: epoxy. 3. substrate material: epoxy laminate 0.25 thickness. double ar glass. 4. lid material: borosilicate glass 0.40.4mm thickness refractive index at 20c = 1.5255 @ 546 nm and 1.5231 @ 588 nm. double side ar coating: 530-570nm r<1%; 420-700nm r<2%. 5. image sensor die: 0.2 thickness. 6. solder ball material: sac 305 (95% sn, 3% ag, 0.5% cu). dimensions apply to sold er balls post reflow. pre-reflow ball is ? 0.5 on a ? 0.4 smd ball pad. ibga63 9x9 case 503ah issue o date 30 dec 201 4
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make change s without further notice to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purp ose, nor does scillc as sume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time . all operating parameters, in cluding typicals must be va lidated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications inte nded to support or sus tain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purch ase or use scillc prod ucts for any such uni ntended or unau thorized applic ation, buyer shall indemnify and hol d scillc and its officer s, employees, subsid iaries, affiliates, and distributors harmless against all claims, costs, damages, and ex penses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportun ity/affirmative ac tion employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. ar0141cs: 1/4-inch digital image sensor package drawings ar0141cs/d rev. 6, 4/16 en 64 ?semiconductor components industries, llc, 2016 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. 7. maximum rotation of optical area relative to package edges: 0.75 . maximum tilt of optical area relati ve to substrate plane d: 25 microns. maximum tilt of cover glass relative to optical area plane e: 5 microns .

▲Up To Search▲

Price & Availability of AR0141CS2M00SUEA0-DPBR

	To Download AR0141CS2M00SUEA0-DPBR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .